? lifimage.wipe Index: Makefile =================================================================== RCS file: /var/cvs/linux-2.6/Makefile,v retrieving revision 1.292 diff -u -p -r1.292 Makefile --- Makefile 3 Nov 2004 00:57:49 -0000 1.292 +++ Makefile 8 Nov 2004 01:58:21 -0000 @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 10 -EXTRAVERSION =-rc1-pa10 +EXTRAVERSION =-rc1-pa11 NAME=Woozy Numbat # *DOCUMENTATION* Index: arch/parisc/kernel/pci-dma.c =================================================================== RCS file: /var/cvs/linux-2.6/arch/parisc/kernel/pci-dma.c,v retrieving revision 1.6 diff -u -p -r1.6 pci-dma.c --- arch/parisc/kernel/pci-dma.c 18 Aug 2004 20:21:40 -0000 1.6 +++ arch/parisc/kernel/pci-dma.c 8 Nov 2004 01:58:25 -0000 @@ -32,18 +32,6 @@ #include #include -#ifdef DEBUG_PCI -#undef ASSERT -#define ASSERT(expr) \ - if(!(expr)) { \ - printk("\n%s:%d: Assertion " #expr " failed!\n", \ - __FILE__, __LINE__); \ - panic(#expr); \ - } -#else -#define ASSERT(expr) -#endif - static struct proc_dir_entry * proc_gsc_root = NULL; static int pcxl_proc_info(char *buffer, char **start, off_t offset, int length); @@ -259,10 +247,6 @@ pcxl_alloc_range(size_t size) u_long mask, flags; unsigned int pages_needed = size >> PAGE_SHIFT; - ASSERT(pages_needed); - ASSERT((pages_needed * PAGE_SIZE) < DMA_CHUNK_SIZE); - ASSERT(pages_needed < (BITS_PER_LONG - PAGE_SHIFT)); - mask = (u_long) -1L; mask >>= BITS_PER_LONG - pages_needed; @@ -306,7 +290,7 @@ resource_found: #define PCXL_FREE_MAPPINGS(idx, m, size) \ u##size *res_ptr = (u##size *)&(pcxl_res_map[(idx) + (((size >> 3) - 1) & (~((size >> 3) - 1)))]); \ - ASSERT((*res_ptr & m) == m); \ + /* BUG_ON((*res_ptr & m) != m); */ \ *res_ptr &= ~m; /* @@ -319,10 +303,6 @@ pcxl_free_range(unsigned long vaddr, siz unsigned int res_idx = (vaddr - pcxl_dma_start) >> (PAGE_SHIFT + 3); unsigned int pages_mapped = size >> PAGE_SHIFT; - ASSERT(pages_mapped); - ASSERT((pages_mapped * PAGE_SIZE) < DMA_CHUNK_SIZE); - ASSERT(pages_mapped < (BITS_PER_LONG - PAGE_SHIFT)); - mask = (u_long) -1L; mask >>= BITS_PER_LONG - pages_mapped; Index: drivers/parisc/iosapic.c =================================================================== RCS file: /var/cvs/linux-2.6/drivers/parisc/iosapic.c,v retrieving revision 1.10 diff -u -p -r1.10 iosapic.c --- drivers/parisc/iosapic.c 3 Nov 2004 00:57:49 -0000 1.10 +++ drivers/parisc/iosapic.c 8 Nov 2004 01:58:26 -0000 @@ -189,31 +189,9 @@ #ifdef DEBUG_IOSAPIC -static char assert_buf[128]; - -static int -assert_failed (char *a, char *f, int l) -{ - sprintf(assert_buf, - "ASSERT(%s) failed!\nline %d in %s\n", - a, /* assertion text */ - l, /* line number */ - f); /* file name */ - panic(assert_buf); - return 0; -} - -#undef ASSERT -#define ASSERT(EX) { if (!(EX)) assert_failed(# EX, __FILE__, __LINE__); } - #define DBG(x...) printk(x) - #else /* DEBUG_IOSAPIC */ - #define DBG(x...) -#undef ASSERT -#define ASSERT(EX) - #endif /* DEBUG_IOSAPIC */ #ifdef DEBUG_IOSAPIC_IRT @@ -351,7 +329,7 @@ iosapic_load_irt(unsigned long cell_num, /* get PCI INT routing table */ status = pdc_pat_get_irt(table, cell_num); DBG("pdc_pat_get_irt: %ld\n", status); - ASSERT(status == PDC_OK); + BUG_ON(status != PDC_OK); } else { /* ** C3000/J5000 (and similar) platforms with Sprockets PDC @@ -667,7 +645,7 @@ iosapic_fixup_irq(void *isi_obj, struct pcidev->irq = isi->isi_region->data.irqbase + isi_line; /* get vector info for this input line */ - ASSERT(NULL != isi->isi_vector); + BUG_ON(NULL == isi->isi_vector); vi = &(isi->isi_vector[isi_line]); DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi); @@ -692,15 +670,14 @@ iosapic_fixup_irq(void *isi_obj, struct /* enable_irq() will use txn_* to program IRdT */ vi->txn_addr = txn_alloc_addr(vi->txn_irq); vi->txn_data = txn_alloc_data(vi->txn_irq, 8); - ASSERT(vi->txn_data < 256); /* matches 8 above */ + BUG_ON(vi->txn_data >= 256); /* matches 8 above */ tmp = request_irq(vi->txn_irq, iosapic_interrupt, 0, vi->name, vi); - ASSERT(tmp == 0); + WARN_ON(tmp != 0); vi->eoi_addr = (u32 *) (isi->isi_hpa + IOSAPIC_REG_EOI); vi->eoi_data = cpu_to_le32(vi->txn_data); - ASSERT(NULL != isi->isi_region); DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n", PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->irq), @@ -726,8 +703,6 @@ iosapic_wr_irt_entry(struct vector_info { struct iosapic_info *isp = vi->iosapic; - ASSERT(NULL != isp); - ASSERT(0 != isp->isi_hpa); DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %p 0x%x 0x%x\n", vi->irqline, isp->isi_hpa, @@ -755,7 +730,6 @@ iosapic_set_irt_data( struct vector_info { u32 mode = 0; struct irt_entry *p = vi->irte; - ASSERT(NULL != vi->irte); if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO) mode |= IOSAPIC_IRDT_PO_LOW; @@ -768,7 +742,6 @@ iosapic_set_irt_data( struct vector_info ** PA doesn't support EXTINT or LPRIO bits. */ - ASSERT(vi->txn_data); *dp0 = mode | (u32) vi->txn_data; /* @@ -846,12 +819,11 @@ iosapic_enable_irq(void *dev, int irq) struct vector_info *vi = &(((struct vector_info *) dev)[irq]); u32 d0, d1; - ASSERT(NULL != vi); - ASSERT(NULL != vi->irte); + BUG_ON(NULL != vi->irte); /* data is initialized by fixup_irq */ - ASSERT(0 < vi->txn_irq); - ASSERT(0UL != vi->txn_data); + BUG_ON(0 == vi->txn_irq); + BUG_ON(0UL == vi->txn_data); iosapic_set_irt_data(vi, &d0, &d1); iosapic_wr_irt_entry(vi, d0, d1); @@ -945,9 +917,8 @@ iosapic_register(unsigned long hpa) ** Search the IRT and ignore iosapic's which aren't ** in the IRT. */ - ASSERT(NULL != irte); /* always have built-in devices */ for (cnt=0; cnt < irt_num_entry; cnt++, irte++) { - ASSERT(IRT_IOSAPIC_TYPE == irte->entry_type); + WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type); /* ** We need sign extension of the hpa on 32-bit kernels. ** The address in the IRT is *always* 64 bit and really @@ -997,7 +968,7 @@ iosapic_register(unsigned long hpa) &iosapic_irq_ops, isi->isi_name, (void *) isi->isi_vector); - ASSERT(NULL != isi->isi_region); + BUG_ON(NULL == isi->isi_region); return ((void *) isi); } @@ -1009,7 +980,6 @@ iosapic_prt_irt(void *irt, long num_entr { unsigned int i, *irp = (unsigned int *) irt; - ASSERT(NULL != irt); printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry); @@ -1023,8 +993,6 @@ iosapic_prt_irt(void *irt, long num_entr static void iosapic_prt_vi(struct vector_info *vi) { - ASSERT(NULL != vi); - printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi); printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status); printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq); @@ -1038,7 +1006,6 @@ iosapic_prt_vi(struct vector_info *vi) static void iosapic_prt_isi(struct iosapic_info *isi) { - ASSERT(NULL != isi); printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi); printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa); printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status); Index: drivers/parisc/lba_pci.c =================================================================== RCS file: /var/cvs/linux-2.6/drivers/parisc/lba_pci.c,v retrieving revision 1.18 diff -u -p -r1.18 lba_pci.c --- drivers/parisc/lba_pci.c 3 Nov 2004 00:57:49 -0000 1.18 +++ drivers/parisc/lba_pci.c 8 Nov 2004 01:58:27 -0000 @@ -90,18 +90,6 @@ #define DBG_PAT(x...) #endif -#ifdef DEBUG_LBA -#undef ASSERT -#define ASSERT(expr) \ - if(!(expr)) { \ - printk("\n%s:%d: Assertion " #expr " failed!\n", \ - __FILE__, __LINE__); \ - panic(#expr); \ - } -#else -#define ASSERT(expr) -#endif - /* ** Config accessor functions only pass in the 8-bit bus number and not @@ -185,7 +173,7 @@ #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */ /* non-postable I/O port space, densely packed */ -#define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL) +#define LBA_PORT_BASE ((void __iomem *)(PCI_F_EXTEND | 0xfee00000UL)) #define ELROY_HVERS 0x782 #define MERCURY_HVERS 0x783 @@ -262,13 +250,13 @@ static u32 lba_t32; #define WRITE_U16(value, addr) __raw_writew(value, addr) #define WRITE_U32(value, addr) __raw_writel(value, addr) -#define READ_REG8(addr) readb(addr) -#define READ_REG16(addr) readw(addr) -#define READ_REG32(addr) readl(addr) -#define READ_REG64(addr) readq(addr) -#define WRITE_REG8(value, addr) writeb(value, addr) -#define WRITE_REG16(value, addr) writew(value, addr) -#define WRITE_REG32(value, addr) writel(value, addr) +#define READ_REG8(addr) readb((void __iomem *) addr) +#define READ_REG16(addr) readw((void __iomem *) addr) +#define READ_REG32(addr) readl((void __iomem *) addr) +#define READ_REG64(addr) readq((void __iomem *) addr) +#define WRITE_REG8(value, addr) writeb(value, (void __iomem *) addr) +#define WRITE_REG16(value, addr) writew(value, (void __iomem *) addr) +#define WRITE_REG32(value, addr) writel(value, (void __iomem *) addr) #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8)) @@ -321,10 +309,6 @@ lba_device_present( u8 bus, u8 dfn, stru u8 first_bus = d->hba.hba_bus->secondary; u8 last_sub_bus = d->hba.hba_bus->subordinate; - ASSERT(bus >= first_bus); - ASSERT(bus <= last_sub_bus); - ASSERT((bus - first_bus) < LBA_MAX_NUM_BUSES); - if ((bus < first_bus) || (bus > last_sub_bus) || ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) @@ -443,7 +427,7 @@ lba_device_present( u8 bus, u8 dfn, stru #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \ WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ - lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR) + lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); #define LBA_CFG_ADDR_SETUP(d, addr) { \ WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ @@ -454,7 +438,7 @@ lba_device_present( u8 bus, u8 dfn, stru * Read address register to ensure that LBA is the bus master, \ * which implies that DMA traffic has stopped when DMA arb is off. \ */ \ - lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ + lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ } @@ -486,33 +470,18 @@ lba_rd_cfg(struct lba_device *d, u32 tok u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */ u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */ - ASSERT((size == sizeof(u8)) || - (size == sizeof(u16)) || - (size == sizeof(u32))); - - if ((size != sizeof(u8)) && - (size != sizeof(u16)) && - (size != sizeof(u32))) { - return(data); - } - LBA_CFG_SETUP(d, tok); LBA_CFG_PROBE(d, tok); LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); if (!error) { + void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; + LBA_CFG_ADDR_SETUP(d, tok | reg); switch (size) { - case sizeof(u8): - data = (u32) READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 3)); - break; - case sizeof(u16): - data = (u32) READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 2)); - break; - case sizeof(u32): - data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA); - break; - default: - break; /* leave data as -1 */ + case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break; + case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break; + case 4: data = READ_REG32(data_reg); break; + default: return ~0; } } LBA_CFG_RESTORE(d, d->hba.base_addr); @@ -520,48 +489,114 @@ lba_rd_cfg(struct lba_device *d, u32 tok } -#if USE_PAT_PDC_CFG +static int lba_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) +{ + struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); + u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; + u32 tok = LBA_CFG_TOK(local_bus, devfn); + void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; -/* PAT PDC needs to be relocated in order to perform properly. - * tg3 driver does about 1600 PCI Cfg writes to initialize the card. - * On 440Mhz A500, PDC takes ~20ms/write, or ~30 seconds per card. - * On PA8800, that takes about 5ms/write (8 seconds). - * But relocating PDC will burn at least 4MB of RAM. - * Easier/Cheaper to just maintain our own mercury cfg ops. - */ -#define pat_cfg_addr(bus, devfn, addr) (((bus) << 16) | ((devfn) << 8) | (addr)) +/* FIXME: B2K/C3600 workaround is always use old method... */ + /* if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) */ { + /* original - Generate config cycle on broken elroy + with risk we will miss PCI bus errors. */ + *data = lba_rd_cfg(d, tok, pos, size); + DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data); + return(*data == ~0U); + } -static int pat_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) -{ - int tok = pat_cfg_addr(bus->number, devfn, pos); - u32 tmp; - int ret = pdc_pat_io_pci_cfg_read(tok, size, &tmp); + if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) + { + DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos); + /* either don't want to look or know device isn't present. */ + *data = ~0U; + return(0); + } + + /* Basic Algorithm + ** Should only get here on fully working LBA rev. + ** This is how simple the code should have been. + */ + LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); + switch(size) { + case 1: *data = READ_REG8 (data_reg + (pos & 3)); break; + case 2: *data = READ_REG16(data_reg + (pos & 2)); break; + case 4: *data = READ_REG32(data_reg); break; + } + DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data); + return(*data == ~0U); +} - DBG_CFG("%s(%d:%d.%d+0x%02x) -> 0x%x %d\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, tmp, ret); +static void +lba_wr_cfg( struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) +{ + int error = 0; + u32 arb_mask = 0; + u32 error_config = 0; + u32 status_control = 0; + void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; + + LBA_CFG_SETUP(d, tok); + LBA_CFG_ADDR_SETUP(d, tok | reg); switch (size) { - case 1: *data = (u8) tmp; return (tmp == (u8) ~0); - case 2: *data = (u16) tmp; return (tmp == (u16) ~0); - case 4: *data = (u32) tmp; return (tmp == (u32) ~0); + case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break; + case 2: WRITE_REG16(data, data_reg + (reg & 2)); break; + case 4: WRITE_REG32(data, data_reg); break; } - *data = ~0; - return (ret); + LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); + LBA_CFG_RESTORE(d, d->hba.base_addr); } -static int pat_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) + +/* + * LBA 4.0 config write code implements non-postable semantics + * by doing a read of CONFIG ADDR after the write. + */ + +static int lba_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) { - int tok = pat_cfg_addr(bus->number, devfn, pos); - int ret = pdc_pat_io_pci_cfg_write(tok, size, data); + struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); + u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; + u32 tok = LBA_CFG_TOK(local_bus,devfn); - DBG_CFG("%s(%d:%d.%d+0x%02x, 0x%lx/%d)\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, data, size); - return (ret); + BUG_ON((tok & 0xff) != 0); + WARN_ON(pos >= 0x100); + + if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) { + /* Original Workaround */ + lba_wr_cfg(d, tok, pos, (u32) data, size); + DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data); + return 0; + } + + if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) { + DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data); + return 1; /* New Workaround */ + } + + DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data); + + /* Basic Algorithm */ + LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); + switch(size) { + case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); + break; + case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); + break; + case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); + break; + } + /* flush posted write */ + lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); + return 0; } -static struct pci_ops pat_cfg_ops = { - .read = pat_cfg_read, - .write = pat_cfg_write, + +static struct pci_ops lba_cfg_ops = { + .read = lba_cfg_read, + .write = lba_cfg_write, }; -#endif #ifdef CONFIG_PARISC64 @@ -604,8 +639,8 @@ static int mercury_cfg_write(struct pci_ u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; u32 tok = LBA_CFG_TOK(local_bus,devfn); - ASSERT((tok & 0xff) == 0); - ASSERT(pos < 0x100); + BUG_ON((tok & 0xff) != 0); + WARN_ON(pos >= 0x100); DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data); @@ -636,133 +671,49 @@ static struct pci_ops mercury_cfg_ops = #endif /* CONFIG_PARISC64 */ -static int lba_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) -{ - struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); - u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; - u32 tok = LBA_CFG_TOK(local_bus, devfn); -/* FIXME: B2K/C3600 workaround is always use old method... */ - /* if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) */ { - /* original - Generate config cycle on broken elroy - with risk we will miss PCI bus errors. */ - *data = lba_rd_cfg(d, tok, pos, size); - DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data); - return(*data == ~0U); - } - - if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) - { - DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos); - /* either don't want to look or know device isn't present. */ - *data = ~0U; - return(0); - } - - /* Basic Algorithm - ** Should only get here on fully working LBA rev. - ** This is how simple the code should have been. - */ - LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); - switch(size) { - case 1: *(u8 *) data = READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); - break; - case 2: *(u16 *) data = READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); - break; - case 4: *(u32 *) data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA); - break; - } - DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data); - return(*data == ~0U); -} +#if USE_PAT_PDC_CFG +/* PAT PDC needs to be relocated in order to perform properly. + * tg3 driver does about 1600 PCI Cfg writes to initialize the card. + * On 440Mhz A500, PDC takes ~20ms/write, or ~30 seconds per card. + * On PA8800, that takes about 5ms/write (8 seconds). + * But relocating PDC will burn at least 4MB of RAM. + * Easier/Cheaper to just maintain our own mercury cfg ops. + */ +#define pat_cfg_addr(bus, devfn, addr) (((bus) << 16) | ((devfn) << 8) | (addr)) -static void -lba_wr_cfg( struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) +static int pat_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) { - int error = 0; - u32 arb_mask = 0; - u32 error_config = 0; - u32 status_control = 0; + int tok = pat_cfg_addr(bus->number, devfn, pos); + u32 tmp; + int ret = pdc_pat_io_pci_cfg_read(tok, size, &tmp); - ASSERT((size == sizeof(u8)) || - (size == sizeof(u16)) || - (size == sizeof(u32))); - - if ((size != sizeof(u8)) && - (size != sizeof(u16)) && - (size != sizeof(u32))) { - return; - } + DBG_CFG("%s(%d:%d.%d+0x%02x) -> 0x%x %d\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, tmp, ret); - LBA_CFG_SETUP(d, tok); - LBA_CFG_ADDR_SETUP(d, tok | reg); switch (size) { - case sizeof(u8): - WRITE_REG8((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA + (reg&3)); - break; - case sizeof(u16): - WRITE_REG16((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA +(reg&2)); - break; - case sizeof(u32): - WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); - break; - default: - break; + case 1: *data = (u8) tmp; return (tmp == (u8) ~0); + case 2: *data = (u16) tmp; return (tmp == (u16) ~0); + case 4: *data = (u32) tmp; return (tmp == (u32) ~0); } - LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); - LBA_CFG_RESTORE(d, d->hba.base_addr); + *data = ~0; + return (ret); } - -/* - * LBA 4.0 config write code implements non-postable semantics - * by doing a read of CONFIG ADDR after the write. - */ - -static int lba_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) +static int pat_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) { - struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); - u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; - u32 tok = LBA_CFG_TOK(local_bus,devfn); - - ASSERT((tok & 0xff) == 0); - ASSERT(pos < 0x100); - - if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) { - /* Original Workaround */ - lba_wr_cfg(d, tok, pos, (u32) data, size); - DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data); - return 0; - } - - if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) { - DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data); - return 1; /* New Workaround */ - } - - DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data); + int tok = pat_cfg_addr(bus->number, devfn, pos); + int ret = pdc_pat_io_pci_cfg_write(tok, size, data); - /* Basic Algorithm */ - LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); - switch(size) { - case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); - break; - case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); - break; - case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); - break; - } - /* flush posted write */ - lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); - return 0; + DBG_CFG("%s(%d:%d.%d+0x%02x, 0x%lx/%d)\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, data, size); + return (ret); } - -static struct pci_ops lba_cfg_ops = { - .read = lba_cfg_read, - .write = lba_cfg_write, +static struct pci_ops pat_cfg_ops = { + .read = pat_cfg_read, + .write = pat_cfg_write, }; +#endif static void @@ -1074,7 +1025,6 @@ LBA_PORT_IN(32, 0) #define LBA_PORT_OUT(size, mask) \ static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ { \ - ASSERT(d != NULL); \ DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \ WRITE_REG##size(val, LBA_PORT_BASE + addr); \ if (LBA_DEV(d)->hw_rev < 3) \ @@ -1305,7 +1255,7 @@ lba_legacy_resources(struct parisc_devic ** PCI bus walk *should* end up with the same result. ** FIXME: But we don't have sanity checks in PCI or LBA. */ - lba_num = READ_REG32(pa_dev->hpa + LBA_FW_SCRATCH); + lba_num = READ_REG32((void __iomem *) pa_dev->hpa + LBA_FW_SCRATCH); r = &(lba_dev->hba.bus_num); r->name = "LBA PCI Busses"; r->start = lba_num & 0xff; @@ -1386,7 +1336,7 @@ lba_legacy_resources(struct parisc_devic * * All is well now. */ - r->start = (long) READ_REG32(pa_dev->hpa + LBA_LMMIO_BASE); + r->start = (long) READ_REG32((void __iomem *) pa_dev->hpa + LBA_LMMIO_BASE); if (r->start & 1) { unsigned long rsize; @@ -1394,7 +1344,7 @@ lba_legacy_resources(struct parisc_devic /* mmio_mask also clears Enable bit */ r->start &= mmio_mask; r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); - rsize = ~ READ_REG32(pa_dev->hpa + LBA_LMMIO_MASK); + rsize = ~ READ_REG32((void __iomem *) pa_dev->hpa + LBA_LMMIO_MASK); /* ** Each rope only gets part of the distributed range. @@ -1432,7 +1382,7 @@ lba_legacy_resources(struct parisc_devic /* See comment which precedes call to sba_directed_lmmio() */ sba_directed_lmmio(pa_dev, r); #else - r->start = READ_REG32(pa_dev->hpa + LBA_ELMMIO_BASE); + r->start = READ_REG32((void __iomem *) pa_dev->hpa + LBA_ELMMIO_BASE); if (r->start & 1) { unsigned long rsize; @@ -1440,7 +1390,7 @@ lba_legacy_resources(struct parisc_devic /* mmio_mask also clears Enable bit */ r->start &= mmio_mask; r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); - rsize = READ_REG32(pa_dev->hpa + LBA_ELMMIO_MASK); + rsize = READ_REG32((void __iomem *) pa_dev->hpa + LBA_ELMMIO_MASK); r->end = r->start + ~rsize; } #endif @@ -1450,8 +1400,8 @@ lba_legacy_resources(struct parisc_devic (int) lba_dev->hba.bus_num.start); r->name = lba_dev->hba.io_name; r->flags = IORESOURCE_IO; - r->start = READ_REG32(pa_dev->hpa + LBA_IOS_BASE) & ~1L; - r->end = r->start + (READ_REG32(pa_dev->hpa + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); + r->start = READ_REG32((void __iomem *) pa_dev->hpa + LBA_IOS_BASE) & ~1L; + r->end = r->start + (READ_REG32((void __iomem *) pa_dev->hpa + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); /* Virtualize the I/O Port space ranges */ lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); @@ -1589,7 +1539,7 @@ lba_driver_probe(struct parisc_device *d char *version; /* Read HW Rev First */ - func_class = READ_REG32(dev->hpa + LBA_FCLASS); + func_class = READ_REG32((void __iomem *) dev->hpa + LBA_FCLASS); if (IS_ELROY(dev)) { func_class &= 0xf; @@ -1649,7 +1599,7 @@ lba_driver_probe(struct parisc_device *d */ lba_dev->hw_rev = func_class; - lba_dev->hba.base_addr = dev->hpa; /* faster access */ + lba_dev->hba.base_addr = (void __iomem *) dev->hpa; /* faster access */ lba_dev->hba.dev = dev; lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */ lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ @@ -1748,12 +1698,12 @@ void __init lba_init(void) void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask) { - unsigned long base_addr = lba->hpa; + void __iomem * base_addr = (void __iomem *) lba->hpa; imask <<= 2; /* adjust for hints - 2 more bits */ - ASSERT((ibase & 0x003fffff) == 0); - ASSERT((imask & 0x003fffff) == 0); + WARN_ON((ibase & 0x003fffff) == 0); + WARN_ON((imask & 0x003fffff) == 0); DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask); WRITE_REG32( imask, base_addr + LBA_IMASK); Index: drivers/parisc/sba_iommu.c =================================================================== RCS file: /var/cvs/linux-2.6/drivers/parisc/sba_iommu.c,v retrieving revision 1.20 diff -u -p -r1.20 sba_iommu.c --- drivers/parisc/sba_iommu.c 31 Oct 2004 03:07:37 -0000 1.20 +++ drivers/parisc/sba_iommu.c 8 Nov 2004 01:58:28 -0000 @@ -58,7 +58,6 @@ extern struct proc_dir_entry * proc_mcki ** Don't even think about messing with it unless you have ** plenty of 710's to sacrifice to the computer gods. :^) */ -#undef DEBUG_SBA_ASSERT #undef DEBUG_SBA_INIT #undef DEBUG_SBA_RUN #undef DEBUG_SBA_RUN_SG @@ -92,19 +91,6 @@ extern struct proc_dir_entry * proc_mcki #define DBG_RES(x...) #endif -#ifdef DEBUG_SBA_ASSERT -#undef ASSERT -#define ASSERT(expr) \ - if(!(expr)) { \ - printk("\n%s:%d: Assertion " #expr " failed!\n", \ - __FILE__, __LINE__); \ - panic(#expr); \ - } -#else -#define ASSERT(expr) -#endif - - #if defined(__LP64__) && !defined(CONFIG_PDC_NARROW) /* "low end" PA8800 machines use ZX1 chipset */ #define ZX1_SUPPORT @@ -547,8 +533,6 @@ sba_search_bitmap(struct ioc *ioc, unsig unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); unsigned long pide = ~0UL; - ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0); - ASSERT(res_ptr < res_end); if (bits_wanted > (BITS_PER_LONG/2)) { /* Search word at a time - no mask needed */ for(; res_ptr < res_end; ++res_ptr) { @@ -631,16 +615,6 @@ sba_alloc_range(struct ioc *ioc, size_t #endif unsigned long pide; - ASSERT(pages_needed); - ASSERT((pages_needed * IOVP_SIZE) <= DMA_CHUNK_SIZE); - ASSERT(pages_needed <= BITS_PER_LONG); - ASSERT(0 == (size & ~IOVP_MASK)); - - /* - ** "seek and ye shall find"...praying never hurts either... - ** ggg sacrifices another 710 to the computer gods. - */ - pide = sba_search_bitmap(ioc, pages_needed); if (pide >= (ioc->res_size << 3)) { pide = sba_search_bitmap(ioc, pages_needed); @@ -707,11 +681,6 @@ sba_free_range(struct ioc *ioc, dma_addr ioc->used_pages -= bits_not_wanted; #endif - ASSERT(m != 0); - ASSERT(bits_not_wanted); - ASSERT((bits_not_wanted * IOVP_SIZE) <= DMA_CHUNK_SIZE); - ASSERT(bits_not_wanted <= BITS_PER_LONG); - ASSERT((*res_ptr & m) == m); /* verify same bits are set */ *res_ptr &= ~m; } @@ -732,8 +701,9 @@ typedef unsigned long space_t; /** * sba_io_pdir_entry - fill in one IO PDIR entry * @pdir_ptr: pointer to IO PDIR entry - * @sid: process Space ID + * @sid: process Space ID - currently only support KERNEL_SPACE * @vba: Virtual CPU address of buffer to map + * @hint: DMA hint set to use for this mapping * * SBA Mapping Routine * @@ -768,7 +738,6 @@ typedef unsigned long space_t; * IOMMU uses little endian for the pdir. */ - void SBA_INLINE sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, unsigned long hint) @@ -776,12 +745,6 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t u64 pa; /* physical address */ register unsigned ci; /* coherent index */ - /* We currently only support kernel addresses. - * fdc instr below will need to reload sr1 with KERNEL_SPACE - * once we try to support direct DMA to user space. - */ - ASSERT(sid == KERNEL_SPACE); - pa = virt_to_phys(vba); pa &= IOVP_MASK; @@ -830,10 +793,6 @@ sba_mark_invalid(struct ioc *ioc, dma_ad */ int off = PDIR_INDEX(iovp)*sizeof(u64)+7; - /* Must be non-zero and rounded up */ - ASSERT(byte_cnt > 0); - ASSERT(0 == (byte_cnt & ~IOVP_MASK)); - #ifdef ASSERT_PDIR_SANITY /* Assert first pdir entry is set */ if (0x80 != (((u8 *) ioc->pdir_base)[off])) { @@ -843,8 +802,6 @@ sba_mark_invalid(struct ioc *ioc, dma_ad if (byte_cnt <= IOVP_SIZE) { - ASSERT( off < ioc->pdir_size); - iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ /* @@ -858,11 +815,7 @@ sba_mark_invalid(struct ioc *ioc, dma_ad u32 t = get_order(byte_cnt) + PAGE_SHIFT; iovp |= t; - ASSERT(t <= 31); /* 2GB! Max value of "size" field */ - do { - /* verify this pdir entry is enabled */ - ASSERT(0x80 == (((u8 *) ioc->pdir_base)[off] & 0x80)); /* clear I/O Pdir entry "valid" bit first */ ((u8 *)(ioc->pdir_base))[off] = 0; off += sizeof(u64); @@ -914,11 +867,7 @@ sba_map_single(struct device *dev, void u64 *pdir_start; int pide; - ASSERT(size > 0); - ASSERT(size <= DMA_CHUNK_SIZE); - ioc = GET_IOC(dev); - ASSERT(ioc); /* save offset bits */ offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; @@ -944,7 +893,6 @@ sba_map_single(struct device *dev, void pdir_start = &(ioc->pdir_base[pide]); while (size > 0) { - ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */ sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", @@ -992,14 +940,10 @@ sba_unmap_single(struct device *dev, dma unsigned long flags; dma_addr_t offset; - ioc = GET_IOC(dev); - ASSERT(ioc); + DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size); + ioc = GET_IOC(dev); offset = iova & ~IOVP_MASK; - - DBG_RUN("%s() iovp 0x%lx/%x\n", - __FUNCTION__, (long) iova, size); - iova ^= offset; /* clear offset bits */ size += offset; size = ROUNDUP(size, IOVP_SIZE); @@ -1131,7 +1075,6 @@ sba_map_sg(struct device *dev, struct sc DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents); ioc = GET_IOC(dev); - ASSERT(ioc); /* Fast path single entry scatterlists. */ if (nents == 1) { @@ -1186,7 +1129,6 @@ sba_map_sg(struct device *dev, struct sc spin_unlock_irqrestore(&ioc->res_lock, flags); - ASSERT(coalesced == filled); DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled); return filled; @@ -1215,7 +1157,6 @@ sba_unmap_sg(struct device *dev, struct __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length); ioc = GET_IOC(dev); - ASSERT(ioc); #ifdef SBA_COLLECT_STATS ioc->usg_calls++; @@ -1460,7 +1401,7 @@ sba_ioc_init_pluto(struct parisc_device ioc->hint_shift_pdir, ioc->hint_mask_pdir); #endif - ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base); + BUG_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); /* build IMASK for IOC and Elroy */ @@ -1575,16 +1516,14 @@ sba_ioc_init(struct parisc_device *sba, ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) */ iov_order = get_order(iova_space_size >> (IOVP_SHIFT-PAGE_SHIFT)); - ASSERT(iov_order <= (30 - IOVP_SHIFT)); /* iova_space_size <= 1GB */ - ASSERT(iov_order >= (20 - IOVP_SHIFT)); /* iova_space_size >= 1MB */ + BUG_ON(iov_order > (30 - IOVP_SHIFT)); /* iova_space_size <= 1GB */ + BUG_ON(iov_order < (20 - IOVP_SHIFT)); /* iova_space_size >= 1MB */ iova_space_size = 1 << (iov_order + IOVP_SHIFT); ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); - ASSERT(pdir_size < 4*1024*1024); /* max pdir size == 2MB */ - /* Verify it's a power of two */ - ASSERT((1 << get_order(pdir_size)) == (pdir_size >> PAGE_SHIFT)); + BUG_ON((1 << get_order(pdir_size)) != (pdir_size >> PAGE_SHIFT)); DBG_INIT("%s() hpa 0x%lx mem %dMB IOV %dMB (%d bits) PDIR size 0x%0x\n", __FUNCTION__, ioc->ioc_hpa, (int) (physmem>>20), @@ -1604,7 +1543,6 @@ sba_ioc_init(struct parisc_device *sba, ioc->hint_shift_pdir, ioc->hint_mask_pdir); #endif - ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base); WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); /* build IMASK for IOC and Elroy */