Index: Makefile =================================================================== RCS file: /var/cvs/linux/Makefile,v retrieving revision 1.389 diff -u -p -r1.389 Makefile --- Makefile 16 Mar 2003 22:17:35 -0000 1.389 +++ Makefile 16 Mar 2003 22:33:53 -0000 @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 4 SUBLEVEL = 20 -EXTRAVERSION = -pa29 +EXTRAVERSION = -pa30 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) Index: drivers/net/tg3.c =================================================================== RCS file: /var/cvs/linux/drivers/net/tg3.c,v retrieving revision 1.4 diff -u -p -r1.4 tg3.c --- drivers/net/tg3.c 29 Nov 2002 02:21:09 -0000 1.4 +++ drivers/net/tg3.c 16 Mar 2003 22:33:53 -0000 @@ -1,8 +1,8 @@ -/* $Id: tg3.c,v 1.43.2.80 2002/03/14 00:10:04 davem Exp $ +/* * tg3.c: Broadcom Tigon3 ethernet driver. * * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) - * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com) + * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@pobox.com) */ #include @@ -33,15 +33,6 @@ #define PCI_DMA_BUS_IS_PHYS 1 #endif -/* Either I can't figure out how they secretly implemented it (ie. RXD flags - * for mini ring, where it should go in NIC sram, and how many entries the NIC - * firmware expects) or it isn't really fully implemented. Perhaps Broadcom - * wants people to pay for a "performance enhanced" version of their firmware + - * binary-only driver that has the mini ring actually implemented. - * These kids today... -DaveM - */ -#define TG3_MINI_RING_WORKS 0 - #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) #define TG3_VLAN_TAG_USED 1 #else @@ -59,8 +50,8 @@ #define DRV_MODULE_NAME "tg3" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "1.2" -#define DRV_MODULE_RELDATE "Nov 14, 2002" +#define DRV_MODULE_VERSION "1.5" +#define DRV_MODULE_RELDATE "Feb 18, 2003" #define TG3_DEF_MAC_MODE 0 #define TG3_DEF_RX_MODE 0 @@ -90,10 +81,6 @@ */ #define TG3_RX_RING_SIZE 512 #define TG3_DEF_RX_RING_PENDING 200 -#if TG3_MINI_RING_WORKS -#define TG3_RX_MINI_RING_SIZE 256 /* ??? */ -#define TG3_DEF_RX_MINI_RING_PENDING 100 -#endif #define TG3_RX_JUMBO_RING_SIZE 256 #define TG3_DEF_RX_JUMBO_RING_PENDING 100 #define TG3_RX_RCB_RING_SIZE 1024 @@ -102,10 +89,6 @@ #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ TG3_RX_RING_SIZE) -#if TG3_MINI_RING_WORKS -#define TG3_RX_MINI_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ - TG3_RX_MINI_RING_SIZE) -#endif #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ TG3_RX_JUMBO_RING_SIZE) #define TG3_RX_RCB_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ @@ -121,9 +104,6 @@ #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64) -#if TG3_MINI_RING_WORKS -#define RX_MINI_PKT_BUF_SZ (256 + tp->rx_offset + 64) -#endif #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64) /* minimum number of free TX descriptors required to wake up TX process */ @@ -132,7 +112,7 @@ static char version[] __devinitdata = DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; -MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@mandrakesoft.com)"); +MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); MODULE_LICENSE("GPL"); MODULE_PARM(tg3_debug, "i"); @@ -157,6 +137,12 @@ static struct pci_device_id tg3_pci_tbl[ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, { PCI_VENDOR_ID_SYSKONNECT, 0x4400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000, @@ -179,6 +165,8 @@ static void tg3_write_indirect_reg32(str spin_unlock_irqrestore(&tp->indirect_lock, flags); } else { writel(val, tp->regs + off); + if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0) + readl(tp->regs + off); } } @@ -229,28 +217,51 @@ static void tg3_enable_ints(struct tg3 * tw32(TG3PCI_MISC_HOST_CTRL, (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000); + tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); - if (tp->hw_status->status & SD_STATUS_UPDATED) { + if (tp->hw_status->status & SD_STATUS_UPDATED) tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); +} + +/* these three netif_xxx funcs should be moved into generic net layer */ +static void netif_poll_disable(struct net_device *dev) +{ + while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) { + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(1); } - tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); } -static inline void tg3_mask_ints(struct tg3 *tp) +static inline void netif_poll_enable(struct net_device *dev) { - tw32(TG3PCI_MISC_HOST_CTRL, - (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); + clear_bit(__LINK_STATE_RX_SCHED, &dev->state); } -static inline void tg3_unmask_ints(struct tg3 *tp) +/* same as netif_rx_complete, except that local_irq_save(flags) + * has already been issued + */ +static inline void __netif_rx_complete(struct net_device *dev) { - tw32(TG3PCI_MISC_HOST_CTRL, - (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); - if (tp->hw_status->status & SD_STATUS_UPDATED) { - tw32(GRC_LOCAL_CTRL, - tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); - } + if (!test_bit(__LINK_STATE_RX_SCHED, &dev->state)) BUG(); + list_del(&dev->poll_list); + clear_bit(__LINK_STATE_RX_SCHED, &dev->state); +} + +static inline void tg3_netif_stop(struct tg3 *tp) +{ + netif_stop_queue(tp->dev); + netif_poll_disable(tp->dev); +} + +static inline void tg3_netif_start(struct tg3 *tp) +{ + netif_poll_enable(tp->dev); + netif_wake_queue(tp->dev); + /* NOTE: unconditional netif_wake_queue is only appropriate + * so long as all callers are assured to have free tx slots + * (such as after tg3_init_hw) + */ } static void tg3_switch_clocks(struct tg3 *tp) @@ -412,7 +423,6 @@ static int tg3_phy_reset(struct tg3 *tp, } static int tg3_setup_phy(struct tg3 *); -static int tg3_halt(struct tg3 *); static int tg3_set_power_state(struct tg3 *tp, int state) { @@ -483,8 +493,6 @@ static int tg3_set_power_state(struct tg tg3_setup_phy(tp); } - tg3_halt(tp); - pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps); if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) { @@ -916,6 +924,20 @@ static int tg3_setup_copper_phy(struct t tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); + /* Some third-party PHYs need to be reset on link going + * down. + * + * XXX 5705 note: This workaround also applies to 5705_a0 + */ + if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && + netif_carrier_ok(tp->dev)) { + tg3_readphy(tp, MII_BMSR, &bmsr); + tg3_readphy(tp, MII_BMSR, &bmsr); + if (!(bmsr & BMSR_LSTATUS)) + tg3_phy_reset(tp, 1); + } + if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { tg3_readphy(tp, MII_BMSR, &bmsr); tg3_readphy(tp, MII_BMSR, &bmsr); @@ -1784,16 +1806,7 @@ static int tg3_alloc_rx_skb(struct tg3 * src_map = &tp->rx_jumbo_buffers[src_idx]; skb_size = RX_JUMBO_PKT_BUF_SZ; break; -#if TG3_MINI_RING_WORKS - case RXD_OPAQUE_RING_MINI: - dest_idx = dest_idx_unmasked % TG3_RX_MINI_RING_SIZE; - desc = &tp->rx_mini[dest_idx]; - map = &tp->rx_mini_buffers[dest_idx]; - if (src_idx >= 0) - src_map = &tp->rx_mini_buffers[src_idx]; - skb_size = RX_MINI_PKT_BUF_SZ; - break; -#endif + default: return -EINVAL; }; @@ -1854,15 +1867,7 @@ static void tg3_recycle_rx(struct tg3 *t src_desc = &tp->rx_jumbo[src_idx]; src_map = &tp->rx_jumbo_buffers[src_idx]; break; -#if TG3_MINI_RING_WORKS - case RXD_OPAQUE_RING_MINI: - dest_idx = dest_idx_unmasked % TG3_RX_MINI_RING_SIZE; - dest_desc = &tp->rx_mini[dest_idx]; - dest_map = &tp->rx_mini_buffers[dest_idx]; - src_desc = &tp->rx_mini[src_idx]; - src_map = &tp->rx_mini_buffers[src_idx]; - break; -#endif + default: return; }; @@ -1938,14 +1943,6 @@ static int tg3_rx(struct tg3 *tp, int bu skb = tp->rx_jumbo_buffers[desc_idx].skb; post_ptr = &tp->rx_jumbo_ptr; } -#if TG3_MINI_RING_WORKS - else if (opaque_key == RXD_OPAQUE_RING_MINI) { - dma_addr = pci_unmap_addr(&tp->rx_mini_buffers[desc_idx], - mapping); - skb = tp->rx_mini_buffers[desc_idx].skb; - post_ptr = &tp->rx_mini_ptr; - } -#endif else { goto next_pkt_nopost; } @@ -1965,7 +1962,6 @@ static int tg3_rx(struct tg3 *tp, int bu len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */ - /* Kill the copy case if we ever get the mini ring working. */ if (len > RX_COPY_THRESHOLD) { int skb_size; @@ -2000,13 +1996,12 @@ static int tg3_rx(struct tg3 *tp, int bu } if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && - (desc->type_flags & RXD_FLAG_TCPUDP_CSUM)) { - skb->csum = htons((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) - >> RXD_TCPCSUM_SHIFT); - skb->ip_summed = CHECKSUM_HW; - } else { + (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && + (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) + >> RXD_TCPCSUM_SHIFT) == 0xffff)) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else skb->ip_summed = CHECKSUM_NONE; - } skb->protocol = eth_type_trans(skb, tp->dev); #if TG3_VLAN_TAG_USED @@ -2051,15 +2046,6 @@ next_pkt_nopost: if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) tr32(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW); } -#if TG3_MINI_RING_WORKS - if (work_mask & RXD_OPAQUE_RING_MINI) { - sw_idx = tp->rx_mini_ptr % TG3_RX_MINI_RING_SIZE; - tw32_mailbox(MAILBOX_RCV_MINI_PROD_IDX + TG3_64BIT_REG_LOW, - sw_idx); - if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) - tr32(MAILBOX_RCV_MINI_PROD_IDX + TG3_64BIT_REG_LOW); - } -#endif return received; } @@ -2068,26 +2054,10 @@ static int tg3_poll(struct net_device *n { struct tg3 *tp = netdev->priv; struct tg3_hw_status *sblk = tp->hw_status; + unsigned long flags; int done; - spin_lock_irq(&tp->lock); - - if (!(tp->tg3_flags & - (TG3_FLAG_USE_LINKCHG_REG | - TG3_FLAG_POLL_SERDES))) { - if (sblk->status & SD_STATUS_LINK_CHG) { - sblk->status = SD_STATUS_UPDATED | - (sblk->status & ~SD_STATUS_LINK_CHG); - tg3_setup_phy(tp); - } - } - - if (sblk->idx[0].tx_consumer != tp->tx_cons) { - spin_lock(&tp->tx_lock); - tg3_tx(tp); - spin_unlock(&tp->tx_lock); - } - + /* run RX thread, within the bounds set by NAPI */ done = 1; if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) { int orig_budget = *budget; @@ -2105,44 +2075,55 @@ static int tg3_poll(struct net_device *n done = 0; } + /* run TX completion thread */ + if (sblk->idx[0].tx_consumer != tp->tx_cons) { + spin_lock(&tp->dev->xmit_lock); + tg3_tx(tp); + spin_unlock(&tp->dev->xmit_lock); + } + + spin_lock_irqsave(&tp->lock, flags); + + /* handle link change and other phy events */ + if (!(tp->tg3_flags & + (TG3_FLAG_USE_LINKCHG_REG | + TG3_FLAG_POLL_SERDES))) { + if (sblk->status & SD_STATUS_LINK_CHG) { + sblk->status = SD_STATUS_UPDATED | + (sblk->status & ~SD_STATUS_LINK_CHG); + tg3_setup_phy(tp); + } + } + + /* if no more work, tell net stack and NIC we're done */ if (done) { - netif_rx_complete(netdev); - tg3_unmask_ints(tp); + __netif_rx_complete(netdev); + tg3_enable_ints(tp); } - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); return (done ? 0 : 1); } -static __inline__ void tg3_interrupt_main_work(struct net_device *dev, struct tg3 *tp) +static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp) { struct tg3_hw_status *sblk = tp->hw_status; - int work_exists = 0; + unsigned int work_exists = 0; + /* check for phy events */ if (!(tp->tg3_flags & (TG3_FLAG_USE_LINKCHG_REG | TG3_FLAG_POLL_SERDES))) { if (sblk->status & SD_STATUS_LINK_CHG) work_exists = 1; } + /* check for RX/TX work to do */ if (sblk->idx[0].tx_consumer != tp->tx_cons || sblk->idx[0].rx_producer != tp->rx_rcb_ptr) work_exists = 1; - if (!work_exists) - return; - - if (netif_rx_schedule_prep(dev)) { - /* NOTE: These writes are posted by the readback of - * the mailbox register done by our caller. - */ - tg3_mask_ints(tp); - __netif_rx_schedule(dev); - } else { - printk(KERN_ERR PFX "%s: Error, poll already scheduled\n", - dev->name); - } + return work_exists; } static void tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs) @@ -2155,15 +2136,32 @@ static void tg3_interrupt(int irq, void spin_lock_irqsave(&tp->lock, flags); if (sblk->status & SD_STATUS_UPDATED) { + /* + * writing any value to intr-mbox-0 clears PCI INTA# and + * chip-internal interrupt pending events. + * writing non-zero to intr-mbox-0 additional tells the + * NIC to stop sending us irqs, engaging "in-intr-handler" + * event coalescing. + */ tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); + /* + * Flush PCI write. This also guarantees that our + * status block has been flushed to host memory. + */ + tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); sblk->status &= ~SD_STATUS_UPDATED; - tg3_interrupt_main_work(dev, tp); - - tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, - 0x00000000); - tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); + if (likely(tg3_has_work(dev, tp))) + netif_rx_schedule(dev); /* schedule NAPI poll */ + else { + /* no work, shared interrupt perhaps? re-enable + * interrupts, and flush that PCI write + */ + tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, + 0x00000000); + tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); + } } spin_unlock_irqrestore(&tp->lock, flags); @@ -2171,23 +2169,23 @@ static void tg3_interrupt(int irq, void static void tg3_init_rings(struct tg3 *); static int tg3_init_hw(struct tg3 *); +static int tg3_halt(struct tg3 *); static void tg3_tx_timeout(struct net_device *dev) { struct tg3 *tp = dev->priv; + unsigned long flags; printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", dev->name); - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + spin_lock_irqsave(&tp->lock, flags); tg3_halt(tp); tg3_init_rings(tp); tg3_init_hw(tp); - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); netif_wake_queue(dev); } @@ -2264,11 +2262,6 @@ static int tigon3_4gb_hwbug_workaround(s return -1; } - /* NOTE: Broadcom's driver botches this case up really bad. - * This is especially true if any of the frag pages - * are in highmem. It will instantly oops in that case. - */ - /* New SKB is guarenteed to be linear. */ entry = *start; new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, @@ -2367,35 +2360,12 @@ static int tg3_start_xmit_4gbug(struct s unsigned int i; u32 len, entry, base_flags, mss; int would_hit_hwbug; - unsigned long flags; len = (skb->len - skb->data_len); - /* No BH disabling for tx_lock here. We are running in BH disabled - * context and TX reclaim runs via tp->poll inside of a software - * interrupt. Rejoice! - * - * Actually, things are not so simple. If we are to take a hw - * IRQ here, we can deadlock, consider: - * - * CPU1 CPU2 - * tg3_start_xmit - * take tp->tx_lock - * tg3_timer - * take tp->lock - * tg3_interrupt - * spin on tp->lock - * spin on tp->tx_lock - * - * So we really do need to disable interrupts when taking - * tx_lock here. - */ - spin_lock_irqsave(&tp->tx_lock, flags); - /* This is a hard error, log it. */ if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) { netif_stop_queue(dev); - spin_unlock_irqrestore(&tp->tx_lock, flags); printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", dev->name); return 1; @@ -2496,7 +2466,7 @@ static int tg3_start_xmit_4gbug(struct s entry, len, last_plus_one, &start, mss)) - goto out_unlock; + goto out; entry = start; } @@ -2535,9 +2505,7 @@ static int tg3_start_xmit_4gbug(struct s if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) netif_stop_queue(dev); -out_unlock: - spin_unlock_irqrestore(&tp->tx_lock, flags); - +out: dev->trans_start = jiffies; return 0; @@ -2548,35 +2516,12 @@ static int tg3_start_xmit(struct sk_buff struct tg3 *tp = dev->priv; dma_addr_t mapping; u32 len, entry, base_flags, mss; - unsigned long flags; len = (skb->len - skb->data_len); - /* No BH disabling for tx_lock here. We are running in BH disabled - * context and TX reclaim runs via tp->poll inside of a software - * interrupt. Rejoice! - * - * Actually, things are not so simple. If we are to take a hw - * IRQ here, we can deadlock, consider: - * - * CPU1 CPU2 - * tg3_start_xmit - * take tp->tx_lock - * tg3_timer - * take tp->lock - * tg3_interrupt - * spin on tp->lock - * spin on tp->tx_lock - * - * So we really do need to disable interrupts when taking - * tx_lock here. - */ - spin_lock_irqsave(&tp->tx_lock, flags); - /* This is a hard error, log it. */ if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) { netif_stop_queue(dev); - spin_unlock_irqrestore(&tp->tx_lock, flags); printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", dev->name); return 1; @@ -2667,16 +2612,26 @@ static int tg3_start_xmit(struct sk_buff if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) netif_stop_queue(dev); - spin_unlock_irqrestore(&tp->tx_lock, flags); - dev->trans_start = jiffies; return 0; } +static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, + int new_mtu) +{ + dev->mtu = new_mtu; + + if (new_mtu > ETH_DATA_LEN) + tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; + else + tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE; +} + static int tg3_change_mtu(struct net_device *dev, int new_mtu) { struct tg3 *tp = dev->priv; + unsigned long flags; if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU) return -EINVAL; @@ -2685,27 +2640,22 @@ static int tg3_change_mtu(struct net_dev /* We'll just catch it later when the * device is up'd. */ - dev->mtu = new_mtu; + tg3_set_mtu(dev, tp, new_mtu); return 0; } - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + tg3_netif_stop(tp); + spin_lock_irqsave(&tp->lock, flags); tg3_halt(tp); - dev->mtu = new_mtu; - - if (new_mtu > ETH_DATA_LEN) - tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE; - else - tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE; + tg3_set_mtu(dev, tp, new_mtu); tg3_init_rings(tp); tg3_init_hw(tp); - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); + tg3_netif_start(tp); return 0; } @@ -2734,20 +2684,7 @@ static void tg3_free_rings(struct tg3 *t dev_kfree_skb_any(rxp->skb); rxp->skb = NULL; } -#if TG3_MINI_RING_WORKS - for (i = 0; i < TG3_RX_MINI_RING_SIZE; i++) { - rxp = &tp->rx_mini_buffers[i]; - if (rxp->skb == NULL) - continue; - pci_unmap_single(tp->pdev, - pci_unmap_addr(rxp, mapping), - RX_MINI_PKT_BUF_SZ - tp->rx_offset, - PCI_DMA_FROMDEVICE); - dev_kfree_skb_any(rxp->skb); - rxp->skb = NULL; - } -#endif for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { rxp = &tp->rx_jumbo_buffers[i]; @@ -2812,9 +2749,6 @@ static void tg3_init_rings(struct tg3 *t /* Zero out all descriptors. */ memset(tp->rx_std, 0, TG3_RX_RING_BYTES); -#if TG3_MINI_RING_WORKS - memset(tp->rx_mini, 0, TG3_RX_MINI_RING_BYTES); -#endif memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES); memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES); @@ -2847,19 +2781,7 @@ static void tg3_init_rings(struct tg3 *t rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT)); } -#if TG3_MINI_RING_WORKS - for (i = 0; i < TG3_RX_MINI_RING_SIZE; i++) { - struct tg3_rx_buffer_desc *rxd; - rxd = &tp->rx_mini[i]; - rxd->idx_len = (RX_MINI_PKT_BUF_SZ - tp->rx_offset - 64) - << RXD_LEN_SHIFT; - rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | - RXD_FLAG_MINI; - rxd->opaque = (RXD_OPAQUE_RING_MINI | - (i << RXD_OPAQUE_INDEX_SHIFT)); - } -#endif if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { struct tg3_rx_buffer_desc *rxd; @@ -2881,14 +2803,6 @@ static void tg3_init_rings(struct tg3 *t break; } -#if TG3_MINI_RING_WORKS - for (i = 0; i < tp->rx_mini_pending; i++) { - if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_MINI, - -1, i) < 0) - break; - } -#endif - if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { for (i = 0; i < tp->rx_jumbo_pending; i++) { if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO, @@ -2913,13 +2827,6 @@ static void tg3_free_consistent(struct t tp->rx_std, tp->rx_std_mapping); tp->rx_std = NULL; } -#if TG3_MINI_RING_WORKS - if (tp->rx_mini) { - pci_free_consistent(tp->pdev, TG3_RX_MINI_RING_BYTES, - tp->rx_mini, tp->rx_mini_mapping); - tp->rx_mini = NULL; - } -#endif if (tp->rx_jumbo) { pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, tp->rx_jumbo, tp->rx_jumbo_mapping); @@ -2955,9 +2862,6 @@ static int tg3_alloc_consistent(struct t { tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) * (TG3_RX_RING_SIZE + -#if TG3_MINI_RING_WORKS - TG3_RX_MINI_RING_SIZE + -#endif TG3_RX_JUMBO_RING_SIZE)) + (sizeof(struct tx_ring_info) * TG3_TX_RING_SIZE), @@ -2965,29 +2869,14 @@ static int tg3_alloc_consistent(struct t if (!tp->rx_std_buffers) return -ENOMEM; -#if TG3_MINI_RING_WORKS - memset(tp->rx_std_buffers, 0, - (sizeof(struct ring_info) * - (TG3_RX_RING_SIZE + - TG3_RX_MINI_RING_SIZE + - TG3_RX_JUMBO_RING_SIZE)) + - (sizeof(struct tx_ring_info) * - TG3_TX_RING_SIZE)); -#else memset(tp->rx_std_buffers, 0, (sizeof(struct ring_info) * (TG3_RX_RING_SIZE + TG3_RX_JUMBO_RING_SIZE)) + (sizeof(struct tx_ring_info) * TG3_TX_RING_SIZE)); -#endif -#if TG3_MINI_RING_WORKS - tp->rx_mini_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE]; - tp->rx_jumbo_buffers = &tp->rx_mini_buffers[TG3_RX_MINI_RING_SIZE]; -#else tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE]; -#endif tp->tx_buffers = (struct tx_ring_info *) &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE]; @@ -2996,14 +2885,6 @@ static int tg3_alloc_consistent(struct t if (!tp->rx_std) goto err_out; -#if TG3_MINI_RING_WORKS - tp->rx_mini = pci_alloc_consistent(tp->pdev, TG3_RX_MINI_RING_BYTES, - &tp->rx_mini_mapping); - - if (!tp->rx_mini) - goto err_out; -#endif - tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, &tp->rx_jumbo_mapping); @@ -3150,6 +3031,7 @@ out: static void tg3_chip_reset(struct tg3 *tp) { u32 val; + u32 flags_save; /* Force NVRAM to settle. * This deals with a chip bug which can result in EEPROM @@ -3166,8 +3048,21 @@ static void tg3_chip_reset(struct tg3 *t } } + /* + * We must avoid the readl() that normally takes place. + * It locks machines, causes machine checks, and other + * fun things. So, temporarily disable the 5701 + * hardware workaround, while we do the reset. + */ + flags_save = tp->tg3_flags; + tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG; + + /* do the reset */ tw32(GRC_MISC_CFG, GRC_MISC_CFG_CORECLK_RESET); + /* restore 5701 hardware bug workaround flag */ + tp->tg3_flags = flags_save; + /* Flush PCI posted writes. The normal MMIO registers * are inaccessible at this time so this is the only * way to make this reliably. I tried to use indirect @@ -4119,8 +4014,6 @@ static int tg3_reset_hw(struct tg3 *tp) * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. * - * ??? No space allocated for mini receive ring? :( - * * The size of each ring is fixed in the firmware, but the location is * configurable. */ @@ -4133,19 +4026,8 @@ static int tg3_reset_hw(struct tg3 *tp) tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC); -#if TG3_MINI_RING_WORKS - tw32(RCVDBDI_MINI_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, - ((u64) tp->rx_mini_mapping >> 32)); - tw32(RCVDBDI_MINI_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, - ((u64) tp->rx_mini_mapping & 0xffffffff)); - tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, - RX_MINI_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT); - tw32(RCVDBDI_MINI_BD + TG3_BDINFO_NIC_ADDR, - NIC_SRAM_RX_MINI_BUFFER_DESC); -#else tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED); -#endif if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) { tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, @@ -4163,9 +4045,6 @@ static int tg3_reset_hw(struct tg3 *tp) /* Setup replenish thresholds. */ tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8); -#if TG3_MINI_RING_WORKS - tw32(RCVBDI_MINI_THRESH, tp->rx_mini_pending / 8); -#endif tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); /* Clear out send RCB ring in SRAM. */ @@ -4213,13 +4092,6 @@ static int tg3_reset_hw(struct tg3 *tp) tp->rx_std_ptr); if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) tr32(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW); -#if TG3_MINI_RING_WORKS - tp->rx_mini_ptr = tp->rx_mini_pending; - tw32_mailbox(MAILBOX_RCV_MINI_PROD_IDX + TG3_64BIT_REG_LOW, - tp->rx_mini_ptr); - if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) - tr32(MAILBOX_RCV_MINI_PROD_IDX + TG3_64BIT_REG_LOW); -#endif if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) tp->rx_jumbo_ptr = tp->rx_jumbo_pending; @@ -4400,6 +4272,12 @@ static int tg3_reset_hw(struct tg3 *tp) if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) tw32(MAC_SERDES_CFG, 0x616000); + /* Prevent chip from dropping frames when flow control + * is enabled. + */ + tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2); + tr32(MAC_LOW_WMARK_MAX_RX_FRAME); + err = tg3_setup_phy(tp); if (err) return err; @@ -4468,9 +4346,10 @@ out: static void tg3_timer(unsigned long __opaque) { struct tg3 *tp = (struct tg3 *) __opaque; + unsigned long flags; - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + spin_lock(&tp->dev->xmit_lock); + spin_lock_irqsave(&tp->lock, flags); /* All of this garbage is because when using non-tagged * IRQ status the mailbox/status_block protocol the chip @@ -4485,9 +4364,11 @@ static void tg3_timer(unsigned long __op } if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { + netif_stop_queue(tp->dev); tg3_halt(tp); tg3_init_rings(tp); tg3_init_hw(tp); + netif_wake_queue(tp->dev); } /* This part only runs once per second. */ @@ -4550,8 +4431,8 @@ static void tg3_timer(unsigned long __op tp->asf_counter = tp->asf_multiplier; } - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock(&tp->dev->xmit_lock); + spin_unlock_irqrestore(&tp->lock, flags); tp->timer.expires = jiffies + tp->timer_offset; add_timer(&tp->timer); @@ -4563,12 +4444,10 @@ static int tg3_open(struct net_device *d int err; spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); tg3_disable_ints(tp); tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; - spin_unlock(&tp->tx_lock); spin_unlock_irq(&tp->lock); /* If you move this call, make sure TG3_FLAG_HOST_TXDS in @@ -4587,7 +4466,6 @@ static int tg3_open(struct net_device *d } spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); tg3_init_rings(tp); @@ -4609,7 +4487,6 @@ static int tg3_open(struct net_device *d tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; } - spin_unlock(&tp->tx_lock); spin_unlock_irq(&tp->lock); if (err) { @@ -4618,16 +4495,14 @@ static int tg3_open(struct net_device *d return err; } - netif_start_queue(dev); - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); tg3_enable_ints(tp); - spin_unlock(&tp->tx_lock); spin_unlock_irq(&tp->lock); + netif_start_queue(dev); + return 0; } @@ -4840,23 +4715,6 @@ static int tg3_open(struct net_device *d readl(rxd + 0x0), readl(rxd + 0x4), readl(rxd + 0x8), readl(rxd + 0xc)); } -#if TG3_MINI_RING_WORKS - for (i = 0; i < 6; i++) { - unsigned long rxd; - - rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_MINI_BUFFER_DESC - + (i * sizeof(struct tg3_rx_buffer_desc)); - printk("DEBUG: NIC RXD_MINI(%d)[0][%08x:%08x:%08x:%08x]\n", - i, - readl(rxd + 0x0), readl(rxd + 0x4), - readl(rxd + 0x8), readl(rxd + 0xc)); - rxd += (4 * sizeof(u32)); - printk("DEBUG: NIC RXD_MINI(%d)[1][%08x:%08x:%08x:%08x]\n", - i, - readl(rxd + 0x0), readl(rxd + 0x4), - readl(rxd + 0x8), readl(rxd + 0xc)); - } -#endif for (i = 0; i < 6; i++) { unsigned long rxd; @@ -4887,7 +4745,6 @@ static int tg3_close(struct net_device * del_timer_sync(&tp->timer); spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); #if 0 tg3_dump_state(tp); #endif @@ -4901,7 +4758,6 @@ static int tg3_close(struct net_device * TG3_FLAG_GOT_SERDES_FLOWCTL); netif_carrier_off(tp->dev); - spin_unlock(&tp->tx_lock); spin_unlock_irq(&tp->lock); free_irq(dev->irq, dev); @@ -5111,6 +4967,7 @@ static void tg3_set_rx_mode(struct net_d static u8 *tg3_get_regs(struct tg3 *tp) { + unsigned long flags; u8 *orig_p = kmalloc(TG3_REGDUMP_LEN, GFP_KERNEL); u8 *p; int i; @@ -5120,8 +4977,8 @@ static u8 *tg3_get_regs(struct tg3 *tp) memset(orig_p, 0, TG3_REGDUMP_LEN); - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + spin_lock_bh(&tp->dev->xmit_lock); + spin_lock_irqsave(&tp->lock, flags); #define __GET_REG32(reg) (*((u32 *)(p))++ = tr32(reg)) #define GET_REG32_LOOP(base,len) \ @@ -5170,8 +5027,8 @@ do { p = orig_p + (reg); \ #undef GET_REG32_LOOP #undef GET_REG32_1 - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); + spin_unlock_bh(&tp->dev->xmit_lock); return orig_p; } @@ -5181,6 +5038,7 @@ static int tg3_ethtool_ioctl (struct net struct tg3 *tp = dev->priv; struct pci_dev *pci_dev = tp->pdev; u32 ethcmd; + unsigned long flags; if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) return -EFAULT; @@ -5268,8 +5126,7 @@ static int tg3_ethtool_ioctl (struct net return -EINVAL; } - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + spin_lock_irqsave(&tp->lock, flags); tp->link_config.autoneg = cmd.autoneg; if (cmd.autoneg == AUTONEG_ENABLE) { @@ -5282,8 +5139,7 @@ static int tg3_ethtool_ioctl (struct net } tg3_setup_phy(tp); - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); return 0; } @@ -5387,19 +5243,11 @@ static int tg3_ethtool_ioctl (struct net struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM }; ering.rx_max_pending = TG3_RX_RING_SIZE - 1; -#if TG3_MINI_RING_WORKS - ering.rx_mini_max_pending = TG3_RX_MINI_RING_SIZE - 1; -#else ering.rx_mini_max_pending = 0; -#endif ering.rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1; ering.rx_pending = tp->rx_pending; -#if TG3_MINI_RING_WORKS - ering.rx_mini_pending = tp->rx_mini_pending; -#else ering.rx_mini_pending = 0; -#endif ering.rx_jumbo_pending = tp->rx_jumbo_pending; ering.tx_pending = tp->tx_pending; @@ -5414,29 +5262,22 @@ static int tg3_ethtool_ioctl (struct net return -EFAULT; if ((ering.rx_pending > TG3_RX_RING_SIZE - 1) || -#if TG3_MINI_RING_WORKS - (ering.rx_mini_pending > TG3_RX_MINI_RING_SIZE - 1) || -#endif (ering.rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || (ering.tx_pending > TG3_TX_RING_SIZE - 1)) return -EINVAL; - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + tg3_netif_stop(tp); + spin_lock_irqsave(&tp->lock, flags); tp->rx_pending = ering.rx_pending; -#if TG3_MINI_RING_WORKS - tp->rx_mini_pending = ering.rx_mini_pending; -#endif tp->rx_jumbo_pending = ering.rx_jumbo_pending; tp->tx_pending = ering.tx_pending; tg3_halt(tp); tg3_init_rings(tp); tg3_init_hw(tp); - netif_wake_queue(tp->dev); - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); + tg3_netif_start(tp); return 0; } @@ -5459,8 +5300,8 @@ static int tg3_ethtool_ioctl (struct net if (copy_from_user(&epause, useraddr, sizeof(epause))) return -EFAULT; - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + tg3_netif_stop(tp); + spin_lock_irqsave(&tp->lock, flags); if (epause.autoneg) tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; else @@ -5476,8 +5317,8 @@ static int tg3_ethtool_ioctl (struct net tg3_halt(tp); tg3_init_rings(tp); tg3_init_hw(tp); - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); + tg3_netif_start(tp); return 0; } @@ -5612,29 +5453,27 @@ static int tg3_ioctl(struct net_device * static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) { struct tg3 *tp = dev->priv; + unsigned long flags; - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + spin_lock_irqsave(&tp->lock, flags); tp->vlgrp = grp; /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ __tg3_set_rx_mode(dev); - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); } static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) { struct tg3 *tp = dev->priv; + unsigned long flags; - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); + spin_lock_irqsave(&tp->lock, flags); if (tp->vlgrp) tp->vlgrp->vlan_devices[vid] = NULL; - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + spin_unlock_irqrestore(&tp->lock, flags); } #endif @@ -5939,7 +5778,8 @@ static int __devinit tg3_phy_probe(struc tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); } - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { + if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && + (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)) { tg3_writephy(tp, 0x1c, 0x8d68); tg3_writephy(tp, 0x1c, 0x8d68); } @@ -6145,15 +5985,33 @@ static int __devinit tg3_get_invariants( pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); } } + + /* Back to back register writes can cause problems on this chip, + * the workaround is to read back all reg writes except those to + * mailbox regs. See tg3_write_indirect_reg32(). + */ + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) + tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG; + if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) tp->tg3_flags |= TG3_FLAG_PCI_32BIT; + /* Chip-specific fixup from Broadcom driver */ + if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && + (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { + pci_state_reg |= PCISTATE_RETRY_SAME_DMA; + pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); + } + /* Force the chip into D0. */ err = tg3_set_power_state(tp, 0); - if (err) + if (err) { + printk(KERN_ERR PFX "(%s) transition to D0 failed\n", + tp->pdev->slot_name); return err; + } /* 5700 B0 chips do not support checksumming correctly due * to hardware bugs. @@ -6161,18 +6019,14 @@ static int __devinit tg3_get_invariants( if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; - /* Regardless of whether checksums work or not, we configure - * the StrongARM chips to not compute the pseudo header checksums - * in either direction. Because of the way Linux checksum support - * works we do not need the chips to do this, and taking the load - * off of the TX/RX onboard StrongARM cpus means that they will not be - * the bottleneck. Whoever wrote Broadcom's driver did not - * understand the situation at all. He could have bothered - * to read Jes's Acenic driver because the logic (and this part of - * the Tigon2 hardware/firmware) is pretty much identical. + /* Pseudo-header checksum is done by hardware logic and not + * the offload processers, so make the chip do the pseudo- + * header checksums on receive. For transmit it is more + * convenient to do the pseudo-header checksum in software + * as Linux does that on transmit for us in all cases. */ tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM; - tp->tg3_flags |= TG3_FLAG_NO_RX_PSEUDO_CSUM; + tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM; /* Derive initial jumbo mode from MTU assigned in * ether_setup() via the alloc_etherdev() call @@ -6250,19 +6104,8 @@ static int __devinit tg3_get_invariants( if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) tp->tg3_flags |= TG3_FLAG_HOST_TXDS; - /* Quick sanity check. Make sure we see an expected - * value here. - */ grc_misc_cfg = tr32(GRC_MISC_CFG); grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; - if (grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5700 && - grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5701 && - grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5702FE && - grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5703 && - grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5703S && - grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5704 && - grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_AC91002A1) - return -ENODEV; if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) { @@ -6270,14 +6113,16 @@ static int __devinit tg3_get_invariants( tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ; } - /* ROFL, you should see Broadcom's driver code implementing - * this, stuff like "if (a || b)" where a and b are always - * mutually exclusive. DaveM finds like 6 bugs today, hello! - */ + /* this one is limited to 10/100 only */ if (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5702FE) tp->tg3_flags |= TG3_FLAG_10_100_ONLY; err = tg3_phy_probe(tp); + if (err) { + printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n", + tp->pdev->slot_name, err); + /* ... but do not return immediately ... */ + } tg3_read_partno(tp); @@ -6331,17 +6176,10 @@ static int __devinit tg3_get_invariants( /* 5700 chips can get confused if TX buffers straddle the * 4GB address boundary in some cases. */ - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { - /* ROFL! Latest Broadcom driver disables NETIF_F_HIGHDMA - * in this case instead of fixing their workaround code. - * - * Like, hey, there is this skb_copy() thing guys, - * use it. Oh I can't stop laughing... - */ + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) tp->dev->hard_start_xmit = tg3_start_xmit_4gbug; - } else { + else tp->dev->hard_start_xmit = tg3_start_xmit; - } tp->rx_offset = 2; if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && @@ -6507,6 +6345,7 @@ static int __devinit tg3_test_dma(struct (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) | (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) | (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT); + /* XXX 5705 note: set MIN_DMA to zero here */ } else { if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) tp->dma_rwctrl = @@ -6524,13 +6363,20 @@ static int __devinit tg3_test_dma(struct (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT); /* Wheee, some more chip bugs... */ - if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1 || - tp->pci_chip_rev_id == CHIPREV_ID_5703_A2 || - tp->pci_chip_rev_id == CHIPREV_ID_5703_A3 || - tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) - tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { + u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); + + if (ccval == 0x6 || ccval == 0x7) + tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; + } } + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) + tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA + << DMA_RWCTRL_MIN_DMA_SHIFT); + /* We don't do this on x86 because it seems to hurt performace. * It does help things on other platforms though. */ @@ -6594,8 +6440,11 @@ static int __devinit tg3_test_dma(struct } #endif - /* Remove this if it causes problems for some boards. */ - tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { + /* Remove this if it causes problems for some boards. */ + tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; + } tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); @@ -6823,7 +6672,6 @@ static int __devinit tg3_init_one(struct tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; #endif spin_lock_init(&tp->lock); - spin_lock_init(&tp->tx_lock); spin_lock_init(&tp->indirect_lock); tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len); @@ -6839,9 +6687,6 @@ static int __devinit tg3_init_one(struct tg3_init_bufmgr_config(tp); tp->rx_pending = TG3_DEF_RX_RING_PENDING; -#if TG3_MINI_RING_WORKS - tp->rx_mini_pending = TG3_DEF_RX_MINI_RING_PENDING; -#endif tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; tp->tx_pending = TG3_DEF_TX_RING_PENDING; @@ -6958,32 +6803,25 @@ static int tg3_suspend(struct pci_dev *p if (!netif_running(dev)) return 0; + tg3_netif_stop(tp); + spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); tg3_disable_ints(tp); - spin_unlock(&tp->tx_lock); spin_unlock_irq(&tp->lock); netif_device_detach(dev); spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); tg3_halt(tp); - spin_unlock(&tp->tx_lock); spin_unlock_irq(&tp->lock); err = tg3_set_power_state(tp, state); if (err) { - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); - tg3_init_rings(tp); tg3_init_hw(tp); - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); - netif_device_attach(dev); + tg3_netif_start(tp); } return err; @@ -7004,15 +6842,10 @@ static int tg3_resume(struct pci_dev *pd netif_device_attach(dev); - spin_lock_irq(&tp->lock); - spin_lock(&tp->tx_lock); - tg3_init_rings(tp); tg3_init_hw(tp); tg3_enable_ints(tp); - - spin_unlock(&tp->tx_lock); - spin_unlock_irq(&tp->lock); + tg3_netif_start(tp); return 0; } Index: drivers/net/tg3.h =================================================================== RCS file: /var/cvs/linux/drivers/net/tg3.h,v retrieving revision 1.4 diff -u -p -r1.4 tg3.h --- drivers/net/tg3.h 29 Nov 2002 02:21:09 -0000 1.4 +++ drivers/net/tg3.h 16 Mar 2003 22:33:53 -0000 @@ -2,7 +2,7 @@ * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. * * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) - * Copyright (C) 2001 Jeff Garzik (jgarzik@mandrakesoft.com) + * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) */ #ifndef _T3_H @@ -25,9 +25,6 @@ #define RX_STD_MAX_SIZE 1536 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */ -#if TG3_MINI_RING_WORKS -#define RX_MINI_MAX_SIZE 256 -#endif /* First 256 bytes are a mirror of PCI config space. */ #define TG3PCI_VENDOR 0x00000000 @@ -116,6 +113,8 @@ #define CHIPREV_ID_5703_A2 0x1002 #define CHIPREV_ID_5703_A3 0x1003 #define CHIPREV_ID_5704_A0 0x2000 +#define CHIPREV_ID_5704_A1 0x2001 +#define CHIPREV_ID_5704_A2 0x2002 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) #define ASIC_REV_5700 0x07 #define ASIC_REV_5701 0x00 @@ -457,6 +456,7 @@ #define RCV_RULE_DISABLE_MASK 0x7fffffff #define MAC_RCV_RULE_CFG 0x00000500 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 +#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 /* 0x504 --> 0x590 unused */ #define MAC_SERDES_CFG 0x00000590 #define MAC_SERDES_STAT 0x00000594 @@ -1139,6 +1139,7 @@ #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 +#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 #define GRC_LOCAL_CTRL 0x00006808 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 @@ -1301,9 +1302,7 @@ #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 -#if TG3_MINI_RING_WORKS #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 -#endif #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 @@ -1453,9 +1452,7 @@ struct tg3_rx_buffer_desc { #define RXD_FLAGS_SHIFT 0 #define RXD_FLAG_END 0x0004 -#if TG3_MINI_RING_WORKS #define RXD_FLAG_MINI 0x0800 -#endif #define RXD_FLAG_JUMBO 0x0020 #define RXD_FLAG_VLAN 0x0040 #define RXD_FLAG_ERROR 0x0400 @@ -1490,9 +1487,7 @@ struct tg3_rx_buffer_desc { #define RXD_OPAQUE_INDEX_SHIFT 0 #define RXD_OPAQUE_RING_STD 0x00010000 #define RXD_OPAQUE_RING_JUMBO 0x00020000 -#if TG3_MINI_RING_WORKS #define RXD_OPAQUE_RING_MINI 0x00040000 -#endif #define RXD_OPAQUE_RING_MASK 0x00070000 }; @@ -1728,31 +1723,69 @@ struct tg3_bufmgr_config { }; struct tg3 { + /* begin "general, frequently-used members" cacheline section */ + /* SMP locking strategy: * * lock: Held during all operations except TX packet * processing. * - * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx + * dev->xmit_lock: Held in tg3_tx, and by upper layer during + * tg3_start_xmit{,_4gbug}, plus assorted driver areas + * that happen to relate to the TX engine. + * * If you want to shut up all asynchronous processing you must - * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must - * be disabled to take 'lock' but only softirq disabling is - * necessary for acquisition of 'tx_lock'. + * acquire both locks, 'xmit_lock' taken before 'lock'. xmit_lock + * is often acquired by the upper layers, so pay attention. IRQs must + * be disabled to take 'lock' but only softirq/BH disabling is + * necessary for acquisition of 'xmit_lock'. + */ spinlock_t lock; - spinlock_t tx_lock; + spinlock_t indirect_lock; + unsigned long regs; + struct net_device *dev; + struct pci_dev *pdev; + + struct tg3_hw_status *hw_status; + dma_addr_t status_mapping; + + u32 msg_enable; + + /* begin "tx thread" cacheline section */ u32 tx_prod; u32 tx_cons; + u32 tx_pending; + + /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */ + struct tg3_tx_buffer_desc *tx_ring; + struct tx_ring_info *tx_buffers; + dma_addr_t tx_desc_mapping; + + /* begin "rx thread" cacheline section */ u32 rx_rcb_ptr; u32 rx_std_ptr; u32 rx_jumbo_ptr; -#if TG3_MINI_RING_WORKS - u32 rx_mini_ptr; + u32 rx_pending; + u32 rx_jumbo_pending; +#if TG3_VLAN_TAG_USED + struct vlan_group *vlgrp; #endif - spinlock_t indirect_lock; + struct tg3_rx_buffer_desc *rx_std; + struct ring_info *rx_std_buffers; + dma_addr_t rx_std_mapping; + + struct tg3_rx_buffer_desc *rx_jumbo; + struct ring_info *rx_jumbo_buffers; + dma_addr_t rx_jumbo_mapping; + + struct tg3_rx_buffer_desc *rx_rcb; + dma_addr_t rx_rcb_mapping; + + /* begin "everything else" cacheline(s) section */ struct net_device_stats net_stats; struct net_device_stats net_stats_prev; unsigned long phy_crc_errors; @@ -1765,6 +1798,7 @@ struct tg3 { #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 #define TG3_FLAG_ENABLE_ASF 0x00000020 +#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 #define TG3_FLAG_POLL_SERDES 0x00000080 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 @@ -1791,8 +1825,6 @@ struct tg3 { #define TG3_FLAG_SPLIT_MODE 0x40000000 #define TG3_FLAG_INIT_COMPLETE 0x80000000 - u32 msg_enable; - u32 split_mode_max_reqs; #define SPLIT_MODE_5704_MAX_REQ 3 @@ -1806,13 +1838,6 @@ struct tg3 { struct tg3_link_config link_config; struct tg3_bufmgr_config bufmgr_config; - u32 rx_pending; -#if TG3_MINI_RING_WORKS - u32 rx_mini_pending; -#endif - u32 rx_jumbo_pending; - u32 tx_pending; - /* cache h/w values, often passed straight to h/w */ u32 rx_mode; u32 tx_mode; @@ -1864,36 +1889,6 @@ struct tg3 { (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \ (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \ (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES) - - unsigned long regs; - struct pci_dev *pdev; - struct net_device *dev; -#if TG3_VLAN_TAG_USED - struct vlan_group *vlgrp; -#endif - - struct tg3_rx_buffer_desc *rx_std; - struct ring_info *rx_std_buffers; - dma_addr_t rx_std_mapping; -#if TG3_MINI_RING_WORKS - struct tg3_rx_buffer_desc *rx_mini; - struct ring_info *rx_mini_buffers; - dma_addr_t rx_mini_mapping; -#endif - struct tg3_rx_buffer_desc *rx_jumbo; - struct ring_info *rx_jumbo_buffers; - dma_addr_t rx_jumbo_mapping; - - struct tg3_rx_buffer_desc *rx_rcb; - dma_addr_t rx_rcb_mapping; - - /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */ - struct tg3_tx_buffer_desc *tx_ring; - struct tx_ring_info *tx_buffers; - dma_addr_t tx_desc_mapping; - - struct tg3_hw_status *hw_status; - dma_addr_t status_mapping; struct tg3_hw_stats *hw_stats; dma_addr_t stats_mapping; Index: include/linux/pci_ids.h =================================================================== RCS file: /var/cvs/linux/include/linux/pci_ids.h,v retrieving revision 1.20 diff -u -p -r1.20 pci_ids.h --- include/linux/pci_ids.h 13 Nov 2002 15:17:03 -0000 1.20 +++ include/linux/pci_ids.h 17 Mar 2003 00:56:26 -0000 @@ -136,6 +136,7 @@ #define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc #define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 #define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33 #define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 #define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 #define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 @@ -143,6 +144,7 @@ #define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 #define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 #define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 +#define PCI_DEVICE_ID_COMPAQ_CISSC 0x0046 #define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 #define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 @@ -172,6 +174,8 @@ #define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623 #define PCI_DEVICE_ID_LSI_FC919 0x0624 #define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625 +#define PCI_DEVICE_ID_LSI_FC929X 0x0626 +#define PCI_DEVICE_ID_LSI_FC919X 0x0628 #define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 #define PCI_DEVICE_ID_LSI_61C102 0x0901 #define PCI_DEVICE_ID_LSI_63C815 0x1000 @@ -265,6 +269,8 @@ #define PCI_DEVICE_ID_ATI_RADEON_RB 0x5145 #define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 +/* RadeonIGP */ +#define PCI_DEVICE_ID_ATI_RADEON_IGP 0xCAB0 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 @@ -288,6 +294,12 @@ #define PCI_DEVICE_ID_NS_87560_USB 0x0012 #define PCI_DEVICE_ID_NS_83815 0x0020 #define PCI_DEVICE_ID_NS_83820 0x0022 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 #define PCI_DEVICE_ID_NS_87410 0xd001 #define PCI_VENDOR_ID_TSENG 0x100c @@ -372,7 +384,7 @@ #define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 #define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 #define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C -#define PCI_DEVIDE_ID_AMD_FE_GATE_700D 0x700D +#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D #define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E #define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F #define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 @@ -387,13 +399,20 @@ #define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 #define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 #define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 -#define PCI_DEVICE_ID_AMD_VIPER_7440 0x7440 -#define PCI_DEVICE_ID_AMD_VIPER_7441 0x7441 -#define PCI_DEVICE_ID_AMD_VIPER_7443 0x7443 -#define PCI_DEVICE_ID_AMD_VIPER_7448 0x7448 -#define PCI_DEVICE_ID_AMD_VIPER_7449 0x7449 +#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440 +# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440 +#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 +# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441 +#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 +# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443 +#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448 +# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448 +#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449 +# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449 +#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462 #define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 #define PCI_DEVICE_ID_AMD_8111_AC97 0x746d +#define PCI_DEVICE_ID_AMD_8131_APIC 0x7450 #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 @@ -477,20 +496,28 @@ #define PCI_DEVICE_ID_SI_635 0x0635 #define PCI_DEVICE_ID_SI_640 0x0640 #define PCI_DEVICE_ID_SI_645 0x0645 -#define PCI_DEVICE_ID_SI_646 0x0646 +#define PCI_DEVICE_ID_SI_646 0x0646 +#define PCI_DEVICE_ID_SI_648 0x0648 #define PCI_DEVICE_ID_SI_650 0x0650 +#define PCI_DEVICE_ID_SI_651 0x0651 +#define PCI_DEVICE_ID_SI_652 0x0652 #define PCI_DEVICE_ID_SI_730 0x0730 #define PCI_DEVICE_ID_SI_630_VGA 0x6300 #define PCI_DEVICE_ID_SI_730_VGA 0x7300 #define PCI_DEVICE_ID_SI_735 0x0735 #define PCI_DEVICE_ID_SI_740 0x0740 #define PCI_DEVICE_ID_SI_745 0x0745 +#define PCI_DEVICE_ID_SI_746 0x0746 +#define PCI_DEVICE_ID_SI_748 0x0748 #define PCI_DEVICE_ID_SI_750 0x0750 +#define PCI_DEVICE_ID_SI_751 0x0751 +#define PCI_DEVICE_ID_SI_752 0x0752 #define PCI_DEVICE_ID_SI_900 0x0900 #define PCI_DEVICE_ID_SI_5107 0x5107 #define PCI_DEVICE_ID_SI_5300 0x5300 #define PCI_DEVICE_ID_SI_5511 0x5511 #define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5518 0x5518 #define PCI_DEVICE_ID_SI_5571 0x5571 #define PCI_DEVICE_ID_SI_5591 0x5591 #define PCI_DEVICE_ID_SI_5597 0x5597 @@ -742,6 +769,9 @@ #define PCI_DEVICE_ID_CMD_670 0x0670 #define PCI_DEVICE_ID_CMD_680 0x0680 +#define PCI_DEVICE_ID_SII_680 0x0680 +#define PCI_DEVICE_ID_SII_3112 0x3112 + #define PCI_VENDOR_ID_VISION 0x1098 #define PCI_DEVICE_ID_VISION_QD8500 0x0001 #define PCI_DEVICE_ID_VISION_QD8580 0x0002 @@ -801,6 +831,14 @@ #define PCI_DEVICE_ID_3COM_3C905TX 0x9050 #define PCI_DEVICE_ID_3COM_3C905T4 0x9051 #define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 +#define PCI_DEVICE_ID_3COM_3CR990 0x9900 +#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 +#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 +#define PCI_DEVICE_ID_3COM_3CR990B 0x9904 +#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905 +#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908 +#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 +#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a #define PCI_VENDOR_ID_SMC 0x10b8 #define PCI_DEVICE_ID_SMC_EPIC100 0x0005 @@ -872,6 +910,7 @@ #define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 #define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C #define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 #define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 @@ -885,6 +924,7 @@ #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 #define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 #define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc #define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 @@ -986,6 +1026,10 @@ #define PCI_DEVICE_ID_VIA_8233C_0 0x3109 #define PCI_DEVICE_ID_VIA_8361 0x3112 #define PCI_DEVICE_ID_VIA_8233A 0x3147 +#define PCI_DEVICE_ID_VIA_P4X333 0x3168 +#define PCI_DEVICE_ID_VIA_8235 0x3177 +#define PCI_DEVICE_ID_VIA_8377_0 0x3189 +#define PCI_DEVICE_ID_VIA_8377_0 0x3189 #define PCI_DEVICE_ID_VIA_86C100A 0x6100 #define PCI_DEVICE_ID_VIA_8231 0x8231 #define PCI_DEVICE_ID_VIA_8231_4 0x8235 @@ -1083,6 +1127,7 @@ #define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000 #define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 #define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 +#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 #define PCI_VENDOR_ID_VMIC 0x114a #define PCI_DEVICE_ID_VMIC_VME 0x7587 @@ -1124,6 +1169,7 @@ #define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 #define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 #define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 #define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB #define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 @@ -1544,6 +1590,9 @@ #define PCI_DEVICE_ID_TIGON3_5702FE 0x164d #define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 #define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 +#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 +#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 #define PCI_VENDOR_ID_SYBA 0x1592 #define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 @@ -1568,6 +1617,9 @@ #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 +#define PCI_VENDOR_ID_HINT 0x3388 +#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + #define PCI_VENDOR_ID_3DLABS 0x3d3d #define PCI_DEVICE_ID_3DLABS_300SX 0x0001 #define PCI_DEVICE_ID_3DLABS_500TX 0x0002 @@ -1629,7 +1681,11 @@ #define PCI_DEVICE_ID_INTEL_82430 0x0486 #define PCI_DEVICE_ID_INTEL_82434 0x04a3 #define PCI_DEVICE_ID_INTEL_I960 0x0960 +#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_82562ET 0x1031 + +#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 + #define PCI_DEVICE_ID_INTEL_82559ER 0x1209 #define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 #define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 @@ -1685,9 +1741,9 @@ #define PCI_DEVICE_ID_INTEL_82801E_2 0x2452 #define PCI_DEVICE_ID_INTEL_82801E_3 0x2453 #define PCI_DEVICE_ID_INTEL_82801E_9 0x2459 -#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b -#define PCI_DEVICE_ID_INTEL_82801E_13 0x245d -#define PCI_DEVICE_ID_INTEL_82801E_14 0x245e +#define PCI_DEVICE_ID_INTEL_82801E_11 0x245B +#define PCI_DEVICE_ID_INTEL_82801E_14 0x245D +#define PCI_DEVICE_ID_INTEL_82801E_15 0x245E #define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 #define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482 #define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 @@ -1728,6 +1784,7 @@ #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82451NX 0x84ca +#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291