Index: arch/parisc/Makefile
===================================================================
RCS file: /var/cvs/linux/arch/parisc/Makefile,v
retrieving revision 1.31
diff -u -p -r1.31 Makefile
--- arch/parisc/Makefile	16 Nov 2002 07:00:31 -0000	1.31
+++ arch/parisc/Makefile	24 Jan 2003 06:57:19 -0000
@@ -32,6 +32,10 @@ CROSS_COMPILE := hppa-linux-
 endif
 endif
 
+ifdef CONFIG_PA20
+CFLAGS += -mpa-risc-2-0
+endif
+
 OFFSET_H := $(TOPDIR)/include/asm-parisc/offset.h
 FINAL_LD=$(CROSS_COMPILE)ld --warn-common --warn-section-align 
 
Index: include/asm-parisc/spinlock_t.h
===================================================================
RCS file: /var/cvs/linux/include/asm-parisc/spinlock_t.h,v
retrieving revision 1.2
diff -u -p -r1.2 spinlock_t.h
--- include/asm-parisc/spinlock_t.h	16 Nov 2002 06:39:42 -0000	1.2
+++ include/asm-parisc/spinlock_t.h	24 Jan 2003 06:57:42 -0000
@@ -32,7 +32,26 @@ typedef struct {
 #define spin_lock_init(x)       do { (x)->lock = 1; } while(0)
 #define spin_is_locked(x)       ((x)->lock == 0)
 #define spin_trylock(x)		(__ldcw(&(x)->lock) != 0)
+#ifdef CONFIG_PA20
+/* PA2.0 is not strongly ordered. ldcw enforces ordering
+ * and we need to make sure ordering is enforced on the unlock too.
+ */
+#define spin_unlock(x) \
+		__asm__ __volatile__ ("stw,o  %%rp,0(%0)" : : "r" (x) : "memory" )
+
+/* 
+ * Alternative in case ,o doesn't work.
+ * Using "sync" messes with caches but is PA1.x compatible.
+ *
+ * #define spin_unlock(x)	__asm__ __volatile__ ("sync\n" \
+ *				"\tstw	1,0(%0)" : : "r" (x) : "memory" )
+ */
+#else
+
+/* PA1.1 is strongly ordered. No issues here. */
 #define spin_unlock(x)		do { (x)->lock = 1; } while(0)
+
+#endif
 
 #define spin_unlock_wait(x)     do { barrier(); } while(((volatile spinlock_t *)(x))->lock == 0)